The invention relates to a semiconductor memory, and more particularly, to set-up of a mode of operation of a semiconductor device.
A synchronous graphic RAM (SGRAM) is used to efficiently process of large amounts of data, such as image data. The SGRAM operates in a number of operational modes which allow it to perform rapid data processing. These modes include a burst mode, a block write mode and the like. The burst operation refers to a read/write operation with respect to a memory core in which information is sequentially accessed by specifying a plurality of column addresses. The block write operation performs a data write operation into a plurality of memory cells using a plurality of column select signals.
Referring to FIG. 1, a conventional SGRAM 10 formed on a single semiconductor substrate, such as a single crystal silicon substrate using a known semiconductor integrated circuit manufacturing technology is known. The SGRAM 10 is connected to a system 32 which provides the SGRAM 10 with a variety of signals such as a clock signal CLK, a distribution enable signal CKE, instruction code signals which constitute operation commands, an address signal A10-A0 (where A10 represents the most significant bit and A0 the least significant bit), a data signal D7-D0 (where D7 represents the most significant bit and D0 the least significant bit), a data mask signal DQM and the like. The SGRAM 10 is controlled in accordance with the various signals from the system 32 in synchronism with the clock signal CLK, in a similar manner as a synchronous DRAM.
The SGRAM 10 includes a memory core 12, a clock buffer 14, an instruction decoder 16, an address buffer register 18, an input/output (I/O) buffer 20, a control signal latch 22 and a column address counter 24. The SGRAM 10 additionally includes operational mode registers such as a mode register 26, a color register 28 and a mask register 30, where the color register 28 and the mask register 30 represent special mode registers. Access information, which defines individual operational modes of the SGRAM 10, is stored or loaded in the mode register 26, the color register 28 and the mask register 30.
The memory core 12 has a multitude of dynamic memory cells which are disposed in a matrix array. The memory core 12 is provided with a row decoder and a column decoder, which are known in the art, and a memory cell has a select terminal connected to a word line and a data input terminal connected to a data line.
The clock buffer 14 receives the clock signal CLK (shown in FIG. 2) and the distribution enable signal CKE from the system 32. In response to the distribution enable signal CKE of a high level (or logical xe2x80x9c1xe2x80x9d level), the clock buffer 14 provides the clock signal CLK to the instruction decoder 16, the address buffer register 18 and the I/O buffer 20.
A summary of the operation of the SGRAM 10 will be given. An operational mode such as the burst operation, the block write operation or the like is initially set up, and a read/write operation then follows in accordance with the operational mode specified. The system 32 provides an address signal A10-A0, as access information which specifies the operational mode, to the SGRAM 10. During the read/write operation, the system 32 provide the address signal A10-A0 to the SGRAM 10 to serve as a row address signal which selects a word line for the memory core 12 and as a column address signal which selects a data line for the memory core 12. All bits in the address signal A10-A0 are used to form the row address signal. Part of the address signals A10-A0, for example, eight bits A7-A0 are used as the column address signal. The three most significant bits A10-A8 of the address signal are not used in the selection of a data line.
The address buffer register 18 receives the clock signal CLK from the clock buffer 14 and receives the address signal A10-A0 in synchronism with the clock signal CLK. During the set-up of an operational mode, the address buffer register 18 loads bits A7-A0 of the address signal into the mode register 26 by way of an internal bus as the access information. The access information in the mode register 26 is also provided to the control signal latch 22. In addition, the address buffer register 18 provides the address signal A10-A0 to the instruction decoder 16. The most significant bit A10 of the address signal is used, for example, to designate one of the mode register 26, the color register 28 and the mask register 30. During the read/write operation, the address buffer register 18 provides the row address signal A10-A0 to the row decoder via an internal bus and also provides the column address signal A7-A0 to the column address counter 24.
The column address counter 24 is provided to implement the burst operation. The column address counter 24 includes a burst counter, not shown, which forms a column address signal, and a burst end counter, not shown, which restricts the number of column address signals formed. The column address signal A7-A0 from the address buffer register 18 is loaded into the burst counter as an initial value. The mode register 26 has stored therein a burst length as access information, which is provided to the burst end counter. In this manner, the burst end counter is preset with burst length information, which is then counted down or decremented to produce an underflow signal. The burst counter is incremented from the initial value until the burst end counter underflows, thus sequentially producing column address signals. The column address signal produced in this manner is decoded by the column decoder within the memory core 12 into a select signal for a particular data line. Data write-in or data read-out into or from a selected memory cell then takes place. After having produced a number of column address signals which depends on the burst length information, the column address counter 24 produces an internal trigger signal TR which indicates the end of the column address signals.
The I/O buffer 20 receives the clock signal CLK from the clock buffer 14 and receives the data signal D7-D0 from the system 32 in accordance with the clock signal CLK. In addition, the I/O buffer 20 delivers the data signal D7-D0 which is read from the memory core 12 to the system 12 in accordance with the clock signal CLK. During the set-up of the operational mode, if either the color register 28 or the mask register 30 is selected, the I/O buffer 20 loads the data signal D7-D0 into the color register 28 or the mask register 30 as access information. During the write operation, the I/O buffer 20 feeds the data signal D7-D0 to the memory core 12. The data signal D7-D0 from the I/O buffer 20 is amplified by a write amplifier, not shown, before it is transmitted onto the data line in the memory core 12 and then that the transmitted signal is written into selected memory cells. During the read operation, data signal D7-D0 from the data line in the memory core 12 is amplified in by main amplifier, not shown, and then delivered by the I/O buffer 20 to the system 32. During the burst operation, the I/O buffer 20 receives one column address from the system 32, and sequentially produces a predetermined number of column address signals inclusive of the received one, which consecutively follow the received column address signal for performing a read/write operation.
The mode register 26 includes a plurality of identically constructed registers, not shown, which correspond to the address signal A10-A0. Access information is loaded into the mode register 26 in accordance with control signals fed from the control signal latch 22. The control signal latch 22 produces control signals for the mode register 26 in response to a predetermined status signal from the instruction decoder 16. For example, the access information loaded into the mode register 26 includes a burst length BL and a CAS latency CL. The burst length BL represents the number of times access is made to the memory core 12 in synchronism with the clock signal CLK. CAS latency CL represents a number of cycles of the clock signal CLK from the time when the column address strobe signal /CAS assumes an active level until data delivery is initiated. For example, when CL=2 and BL=4, the data delivery is commenced in response to the second pulse of the clock signal CLK which occurs after the column address strobe signal /CAS has assumed its active level, and is continued until the fifth pulse of the clock signal CLK since the commencement of the data delivery.
The instruction decoder 16 receives an instruction code signal contained in the operation command signal which is fed from the system 32. The instruction code signal includes a read instruction, a write instruction, and a mode set-up instruction code which is used to set up the operational mode of the SGRAM 10. The mode set-up instruction code corresponds to a particular combination of levels of a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a block write signal DSF.
The instruction decoder 16 receives the clock signal CLK from the clock buffer 14, and receives the instruction code signal from the system 32 and the address signal A10-A0 from the address buffer register 18 in synchronism with the clock signal CLK. The decoder 16 decodes the most significant bit A10 in the address signal as well as the instruction code signal into an internal instruction code, which is delivered to the control signal latch 22.
The operation command additionally includes a register set command, a read command, a write command and a block write command. The register set command includes a mode register set command and a special mode register set command.
When the chip select signal /CS-low, the row address strobe signal /RAS-high, the column address strobe signal /CAS-high, the write enable signal /WE-high and the block write enable signal DSF-low are fed from the system 32, the instruction decoder 16 selects the mode register set command. When the mode register set command is selected, the address signal A10-A0 is loaded into the mode register 26 as access information (operational mode) for the SGRAM 10.
When the chip select signal /CS-low, the row address strobe signal /RAS-high, the column address strobe signal /CAS-high, the write enable signal /WE-high and the block write enable signal DSF-high are fed from the system 32, the instruction decoder 16 selects the special mode register set command. At this time, if the most significant bit A10 of the address signal A10-A0 is a high, data signal D7-D0 is loaded into the color register 28 as access information (operational mode) for the SGRAM 10. Conversely, if the bit A10 is low, the instruction decoder 16 loads data signal D7-D0 into the mask register 30 as access information (operational code) for the SGRAM 10.
The read command controls a read operation in accordance with the access information in the mode register 26, selects a data line in the memory core 12 and activates the I/O buffer 20. When the read command is selected, the mode register 26 stores information relating to the burst operation. When the chip select signal /CS-low, the column address strobe signal /CAS-low, the row address strobe signal /RAS-high, the write enable signal /WE-high and the block write enable signal DSF-low are fed from the system 32, the instruction decoder 16 selects the read command, which is then decoded into an internal instruction code.
Upon receiving the read command (the internal instruction code) from the instruction decoder 16, the control signal latch 22 instructs the memory core 12 to perform a burst read operation which conforms to the burst length information stored in the mode register 26. The address buffer register 18 then feeds the column address signal A7-A0 to the column address counter 24, which uses it as an initial value to produce a number of column address signals which correspond to the burst length and which consecutively follow the initial value in a sequential manner. Data from the memory cells connected to the data line selected by the column address signal are delivered to the system 32 via the I/O buffer 20. The data delivery takes place according to the CAS latency loaded in the mode register 26.
The write command controls a write operation in accordance with the access information in the mode register 26, selects a data line in the memory core 12 and activates the I/O buffer 20. When the write command is selected, a burst operation is set up in the mode register 26. When the chip select signal /CS-low, the column address strobe signal /CAS-low, the write enable signal /WE-low, the row address strobe signal /RAS-high and the block write enable signal DSF-low are fed from the system 32, the instruction decoder 16 selects the write command, which is decoded into an internal instruction code.
Upon receiving the write command (the internal instruction code), the control signal latch 22 instructs the memory core 12 to perform a burst write operation which conforms to the burst length information stored in the mode register 26. The address buffer register 18 feeds the address signal A7-A0 to the column address counter 24 as a column address signal, which is then used as an initial value to produce a number of column address signals which consecutively follow the initial value and which correspond to the burst length. Data signal D7-D0 is fed via the I/O buffer 20 to be written into memory cells in the memory core 12 which are selected by the column address signals.
The block write command controls a write operation in accordance with the access information in the mode register 26, the color register 28 and the mask register 30, and is used to activate the I/O buffer 20. When the chip select signal /CS-low, the column address strobe signal /CAS-low, the write enable signal /WE-low, the row address strobe signal /RAS-high and the block write signal DSF-high are fed from the system 32, the instruction decoder 16 selects the block write command, which is then decoded into an internal instruction code.
Upon receiving the block write command, the control signal latch 22 instructs a block write operation to the color register 28 and the mask register 30 via the mode register 26. The address buffer register 18 then feeds the address signal A10-A0 to the column address counter 24 as a column address signal, which is used therein as an initial value to produce a number of column address signals which consecutively follow the initial value. In this manner, a plurality of data lines which correspond to the plurality of column address signals are simultaneously selected, and the same data is fed to the data lines in a collective manner to be written into corresponding memory cells.
It can be seen from the above description that in order to load access information into the mode register 26, the color register 28 and the mask register 30, it is necessary that the system 32 feeds a signal corresponding to the register set command to the instruction decoder 16 in a similar manner as for the read or the write command.
Referring now to FIG. 2, an operation which follows a read operation in order to modify access information in the mode register 26 will be described. It is assumed that the access information which is loaded in the mode register 26 contains the CAS latency (CL=3) and the burst length (BL=4). A read command is fed to the instruction decoder 16 in response to a first pulse C0 of the clock signal CLK. At a fourth pulse C3, an internal trigger signal TR indicating the termination of the burst operation is produced by the column address counter 24. After the read command is fed, the instruction decoder 16 maintains an output control signal IOE at its high level (or logical xe2x80x9c1xe2x80x9d level) for an interval from a third to a seventh pulse C2-C6. Data read RD1-RD4 on an internal bus is delivered to the system 32 via the I/O buffer 20 during the interval the output control signal IOE assumes its high level.
When the system 32 feeds a register set command in following the read operation, it is preferred for correct data transfer that an interval be provided during which a command is not fed subsequent to the termination of the read operation until a predetermined time interval passes or a predetermined number of pulses in the clock signal CLK are counted after the termination of the read operation. It is also possible to eliminate such time interval and to feed the set command immediately following the seventh pulse C6 of the clock signal CLK, thus at eighth pulse C7, as shown in FIG. 2, while feeding access information to the mode register 26. In FIG. 2, a signal SD represents data corresponding to a mode set-up command.
However, even in such an instance, a time interval must be provided , as may be represented by a predetermined number of pulses, between feeding the register set command and feeding subsequent access information. Thus, subsequent access information would be fed at the tenth cycle C9 or later, thus wasting two or more cycles of the clock signal CLK, which degrades the data transfer efficiency. Accordingly, where access information (operational mode) to be loaded into the mode register 26, the color register 28 and the mask register 30 is frequently changed, there is a degradation in the data transfer rate.
To achieve the above objective, the present invention provide a semiconductor memory for operation in a plurality of operational modes including at least a read, a write and a set up mode, the semiconductor memory comprising: an instruction decoder, receiving an instruction code signal for setting up one of the plurality of operational modes and a mode set-up instruction signal for modifying the operational mode set up by the instruction code signal, for decoding the instruction code signal and the mode set-up instruction signal; at least one register connected to the instruction decoder for storing operational mode information corresponding to the decoded instruction code signal; a memory core for storing data, wherein the memory core is accessed in the operational mode which is set up; and a mode set-up control circuit connected to the instruction decoder, wherein the mode set-up control circuit receives the decoded mode set-up instruction signal and loads corresponding operational mode information into the register in response to the termination of the previously set up operational mode.
The present invention further provide a method of loading operational mode information for a semiconductor memory which is adapted to operate in a plurality of operational modes including at least a read, a write and a set-up mode operation, the method comprising the steps of: loading the operational mode information in a register; collectively providing an instruction code signal which sets up one of the plurality of operational modes in accordance with the operational mode information and a mode set-up instruction signal for modifying the previously set up operational mode; executing an operation specified by the operational mode which is set up; and reloading the operational mode information in accordance with the mode set-up instruction signal immediately after the termination of the operation.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.